For many applications, and particularly in consumer electronic devices, the large and heavy cathode ray tube (CRT) has been replaced by flat panel display types such as liquid crystal display (LCD). A flat panel display contains an array of display elements. Each display element is to receive a signal that represents the picture element (pixel) value to be displayed at that location. In an active matrix array, the pixel signal is applied using a pixel transistor that is coupled to and integrated with the display element. The pixel transistor acts as a switch element. It has a carrier electrode that receives the pixel signal and a control electrode that receives a gate (select) signal. The gate signal may serve to turn on or turn off the transistor so as to selectively apply or “sample” the pixel signal onto the coupled display element. In many instance, the pixel transistor is formed as a thin film transistor (TFT) on the display panel as its substrate.
Typically, thousands or millions of copies of the display element and its associated switch element (e.g., an LCD cell and its associated field effect transistor, FET) are reproduced in the form of an array, on a substrate such as a plane of glass or other light transparent material. The array is overlaid with a grid of data lines and gate lines. The data lines serve to deliver the pixel signals to the carrier electrodes of the transistors and the gate lines serve to apply the gate signals to the control electrodes of the transistors. In other words, each of the data lines is coupled to a respective group of display elements, typically referred to as a column of display elements, while each of the gate lines is coupled to a respective row of display elements.
Each data line is coupled to a data line driver circuit that receives control and pixel signals from a signal generator. The latter translates incoming pixel values (for example, red, green and blue pixel values) into data signals (with appropriate timing). The data line driver then performs the needed voltage level shifting to produce a pixel signal with the needed fan-out (current capability).
As to the gate lines, each gate line is coupled to a gate line driver circuit that receives clock (control) signals from the signal generator. These clocks signals, together with a start or input pulse signal are generated into the domain of a reference clock that is received by the signal generator, along with horizontal and vertical sync signals for defining the scan of a each frame. Each gate driver circuit typically drives a respective gate line. The array of display elements are, in most cases, driven in a horizontal or line-by-line scanning fashion: the desired pixel signals for a selected row of display elements are provided on the data lines; and the selected row of display elements is “enabled” by a pulse that is asserted on the associated gate line, by the gate driver circuit of that gate line. The approach is to scan line-by-line or row-by-row in a vertical direction, until the entire display element array has been “filled” with the pixel values of a single image frame.
The gate driver circuitry has stringent requirements in terms of timing of the transitions in the gate signals that it generates (and that are applied to the gate lines). Due to the nature of the display element array where an entire row of display elements are activated essentially simultaneously (within a single gate signal pulse window), and the relatively large number of rows sometimes, the gate driver circuitry needs to provide precise control of the transitions in these gate drive signals. This is also desirable in view of the relatively high refresh rates of, for example, a 100 Hz display panel, in which the entire array of display elements are refreshed 100 times per second.